In the thin film transistor display, a gate driving signal is generally provided to gates of respective thin film transistors (TFT) of a pixel region through a gate driving circuit. The gate driving circuit can be formed on an array substrate of a liquid crystal display through array process, i.e., gate driver on array (GOA) process. Such integration process not only saves cost, but also has an artistic design where two sides of the liquid crystal panel are symmetrical. At the same time, it saves wiring space of bonding area and fan-out of a gate integrated circuit (IC), so that a design of narrow frame can be realized; furthermore, such integration process can save bonding process in a direction of gate scanning line, so that productivity and yield rate are raised.
The existing gate driving circuit is usually constituted of a plurality of shift registers connected in cascades. Each stage of shift registers is corresponding to one gate line, so that the gate driving circuit scans respective gate lines through respective stages of shift registers respectively. However, in the existing gate driving circuit, each stage of shift register comprises a plurality of switch transistors and occupies a large area, which is disadvantageous for the design of narrow frame.
Therefore, how to provide a gate driving circuit being beneficial for the design of narrow frame is a technical problem that urgently needs to be solved.